Low dropout (LDO) voltage regulators are used in a variety of applications in electronic devices to supply power. These types of voltage regulators can provide a reliable and accurate DC voltage signal for devices sensitive to variations in received power. An LDO regulator provides a low dropout voltage, i.e., a small input-to-output differential voltage, allowing the input voltage to be only a small amount above the desired output voltage, as is desired for low-voltage microprocessors in such applications as portable electronic devices and the like. The fixed output voltage can be provided for varying loads.
The main components of a typical LDO regulator include a power transistor (such as a FET) and a differential amplifier (error amplifier). One input of the error amplifier monitors a percentage of the output, as determined by a resistance divider. The second input to the error amplifier is provided by a voltage reference. If the output voltage rises too high relative to the reference voltage, the signal to the power transistor changes so as to maintain a constant output voltage. If the output voltage is too low, the output voltage is similarly adjusted to a greater value. An output load capacitor is often included to buffer oscillation which may occur in the output voltage depending on provided currents.
In some applications for an LDO voltage regulator, switching output current peaks may occur. For example, when writing or reading a block of memory in a flash memory or electrical eraseable programmable read only memory (EEPROM), current peaks can occur due to the switching of memory circuits connected to the output of the regulator. Current switching peaks may also occur in the use of high speed digital circuits. In such situations, the LDO regulator sources the required current to the load; however, the LDO regulator requires a delay to source this required current. This delay can be caused by the limited bandwidth of the LDO regulator, as well as its limited internal slew-rate. During this delay, the dropout of the output voltage only depends on the output voltage value provided by the output capacitor and is thus not being regulated by the LDO regulator. As a consequence, the output voltage tends to fall down dramatically before the LDO regulator finally can regulate the output voltage to the desired level.
Currently there are two methods that are typically used to limit the dropout of LDO regulators caused by switching current peaks. In one method, the capacitance of the output load capacitor is increased. However, this solution can be unsuitable for applications where the load capacitor is implemented directly on an integrated circuit chip. The total area of the integrated circuit chip already limits the on-chip capacitance value of the capacitor, and a significant increase in the output capacitor value would occupy an even larger area. To accommodate such a larger capacitor would prohibitively increase the cost of the integrated circuit.
In another solution, the bandwidth and slew-rate of the LDO regulator are increased. However, to achieve this higher performance the LDO regulator current consumption must be increased, and higher current consumption is often a major concern when used in such applications as portable devices or battery-powered applications. Thus, in such applications, increasing the LDO bandwidth and slew-rate is typically not a viable option.
Accordingly, an LDO voltage regulator that can sustain higher current peaks at its output without the use of increased load capacitance or higher current consumption of the regulator, would be desirable in many applications.